1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to semiconductor memory devices.
2. Description of the Related Art
In general, a semiconductor memory system has an external memory controller that requests data to be read from or written to a semiconductor memory device. If a read command is given, the memory controller expects valid data to be transmitted via a data bus at a predetermined external clock cycle, i.e., a predetermined latency, after the read command was given. The semiconductor memory device has a clock system that receives an external clock signal and generates a plurality of internal clock signals for internal operations of the semiconductor memory device from the external clock signal. An internal clock system that is well known in the field of semiconductor memory device, and particularly, in the field of dynamic random access memory (DRAM), is a back-timed read clock domain provided in a delay locked loop (hereinafter referred to as “DLL”).
FIG. 1 is a block diagram illustrating a latency control operation of a conventional semiconductor memory device 100. Referring to FIG. 1, the semiconductor memory device 100 includes a command buffer 110, a clock buffer 120, a DLL 130, a latency counter 140, a replica delay unit 150 and a data output buffer 160.
The command buffer 110 receives an external command, e.g., a read command READ, and the clock buffer 120 receives an external clock signal EXCLK. Hereinafter, it is assumed that an external command is a read command READ. The DLL 130 receives the buffered external clock signal and generates an internal clock signal DLLCLK. The semiconductor memory device 100 controls a read latency in response to the read command READ. A read command PREAD output from the command buffer 110 is supplied to the latency counter 140. The latency counter 140 samples the read command PREAD and generates a latency signal LATENCY, in response to the read command PREAD, internal clock signal DLLCLK and a clock signal received from the replica delay unit 150.
The replica delay unit 150 may include a data output buffer replica unit 153 and a command path replica unit 157. The data output buffer replica unit 153 delays the internal clock signal DLLCLK by a delay time tSAC of the data output buffer 160, which is the time between when the internal clock signal DLLCLK enters the data output buffer 160 and data OUT is output from the data output buffer 160. Then the data output buffer replica unit 153 outputs the delayed internal clock signal to the command path replica unit 157. The command path replica unit 157 delays the delayed internal clock signal DLLCLK by a delay time tREAD of the command buffer 110, which is the time between when the read command READ enters the command buffer 110 and a command PREAD is output from the command buffer 110. Thus, the replica delay unit 150 delays the internal clock signal DLLCLK by tSAC+tREAD and then outputs the delayed internal clock signal. The replica delay unit 150 is constructed by a plurality of circuits replicating a tSAC path and a tREAD path. The DLL 130 delays the external clock signal EXCLK so that the internal clock signal DLLCLK can precede the external clock signal EXCLK by the delay tSAC.
The data output buffer 160 generates the output data OUT in response to the latency signal LATENCY and the internal clock signal DLLCLK,
FIG. 2A is a circuit diagram of the latency counter 140 and the replica delay unit 150 illustrated in FIG. 1. FIG. 2B is a timing diagram of signals illustrated in FIG. 2A. Referring to FIGS. 2A and 2B, the latency counter 140 is constructed in a shift register scheme including first through fifth flip-flops 210, 212, 214, 216, and 218. The total number of the first through fifth flip-flops 210 through 218 may vary according to a CAS latency (CL). The replica delay unit 150 includes first through fourth unit delay units 202, 204, 206, and 208. A total amount of time delayed by the first through fourth unit delay units 202 through 208 is tSAC+tREAD as described above. An amount of time tD delayed by each of the first through fourth unit delay units 202 through 208 is (tSAC+tREAD)/(CL−1).
The internal clock signal DLLCLK is input to the first unit delay unit 202 of the replica delay unit 150. The first through fourth unit delay units 202 through 208 are connected in series, and thus, the fourth unit delay unit 208 generates a clock signal P1 obtained by delaying the internal clock signal DLLCLK by tSAC+tREAD as illustrated in FIG. 2B. In the latency counter 140, the first through fifth flip-flops 210 through 218 receive the buffered read command PREAD and then generate a latency signal LATENCY, in response to clock signals P1, P2, P3, P4, and P5 being respectively received from the first through fourth unit delay units 202 through 208. The latency counter 140 samples the buffered read command PREAD in response to the clock signal P1 received from the fourth unit delay unit 208, and then generates the latency signal LATENCY by using the clock signal P5.
The latency counter 140 employing the shift register scheme is advantageous when there are a small number of types of CAS latency CL to be supported but may be disadvantageous in high-speed DRAM that supports a large number of types of CAS latency CL. This is because a delay chain, such as the latency counter 140, may be additionally needed according to the type of CAS latency CL. Thus, the more types of CAS latency CL there are, the greater the number of delay chains. Accordingly, delay tuning may be performed in consideration of changes in process, voltage and/or temperature, and further, layout area may be increased. Furthermore, so that a sufficient timing margin may be secured for each of the flip-flops 210 through 218, an increase in the types of CAS latency CL may result in an increase in a minimum amount of time for accessing a DRAM. As a result, data access speed limits in the DRAM may be determined by the latency counter 140 and not by the speed of reading data from a memory cell.